Chip design is one of the most fascinating application areas of combinatorial optimization. Virtually all classical combinatorial optimization problems, and many new ones, occur naturally as subtasks.
In this talk we will give a short introduction to the area and then focus on interconnect routing, i.e. Steiner tree packing. Mathematical improvements of the last few years have lead to a breakthrough in integrating global signal speed constraints into the Steiner tree packing problem in a practically solvable way. This results in faster and more efficient chips and is currently changing the overall design methodology of the next generation of supercomputer and mainframe processors.
Date: Monday, June 17th , 2019 (starting at 14:00)
Location: Z536 (City)